The present invention is directed to a system which is capable of interconnecting a multiplicity of peripheral devices, of various protocols, to a central processor. The peripheral devices such as terminals or other computers, transfer data in serial data streams. Several differing protocols have been established to initiate, control, verify, and terminate the data transfer between the peripheral devices and the central processor.
In prior art systems, peripheral devices are connected to communication lines and the communication lines are connected to a central processor bus (data channel or data storage). In these systems, a control function exists between a communication line and the central processor and between the communication line and a peripheral device. These controllers execute communication protocol between controllers and execute data exchange procedures between the controller and the central processor.
In prior art systems, when a communication line event occurs; such as series of bits being assembled into a byte, the beginning of the disassembly of a byte into a sequence of bits, or that a control signal has changed its binary state; a signal (request) is generated for the central processor. In systems where a multiplicity of peripheral devices are attempting to gain the attention of the central processor, various techniques such as polling (for requests) or hardware interrupting, enable the peripheral device to have access to the central processor based on the priority assigned to each peripheral device.
The present invention uses software to assemble and disassemble the protocol functions and uses hardware to do the multiplexing. The hardware directs indirect branching of software to permit the software to execute straight lines of software which branch back to hardware upon completion. The present multiplexing processor migrates traditional hardware functions into software routines.
Generally speaking, in prior art systems, the communication lines connected to the peripheral devices are scanned (multiplexed) for a line that is carrying a signal requiring (requesting) access to the central processor bus. Once a line has been found that is requesting bus access, if the priority of the peripheral device connected to that line has an assigned priority which is higher than any other peripheral device requesting access, it is granted exclusive access to the central processor bus until its communication task is completed. When the task is completed, the next highest priority peripheral device is granted access to the central processor bus and this procedure continues until all the requesting peripheral devices have been serviced. In some instances, a busy, high-priority peripheral device, once having gained access, will prevent the access of a lower-priority device thereby providing an unsatisfactory condition. The present invention eliminates the contention of peripheral devices for central processor software programs by synchronizing the central processor to the maximum total information rate of the connected peripheral devices. The basic machine cycle of the central processor is an integer factor of the bit time period of any of the connected communication lines.